1. Field of the Invention
The present invention is directed toward the field of data communications, and more particularly toward a high-speed clock and data recovery circuit.
2. Art Background
Electronic circuits utilize serial data transmission to transmit data among one or more circuits. In general, serial data transmission involves transmitting bits in a single bit stream at a predetermined data rate. The data rate is expressed as the number of bits transmitted per second (“bps”). Typically, to transfer data between circuits, the sending circuit employs a transmitter that modulates and sends data using a local clock. The local clock provides the timing for the bit rate. The receiving circuit employs a receiver to recover the data, and in some eases, the clock. The receiver circuit recovers the serial bit stream of data by sampling the bit stream at the specified data rate.
Techniques have been developed in an attempt to maximize the efficiency of serial data transfer. One such technique recovers the data at the receiver without receiving the sampling clock from the transmitter (i.e., a separate clock is generated at the receiver). Most serial data links that utilize this technique “over sample” the data to recover clock and data. In one over sampling method, the incoming data is first sampled at the bit cycle transition point to determine whether the phase of the clock at the receiver leads or lags the phase of the bit transitions in the serial bit stream. In addition, the serial bit stream is sampled at the center of the bit cycle to determine the state or value of the data for that bit cycle. If the semiconductor technology that implements the receiver is fast enough, the rate of the sampling clock at the receiver is equal to the bit rate. For example, if the bit rate for a serial data link is 40 giga bits per second, then the clock used to sample the data may have a frequency of 40 gigahertz (“GHz”).
Techniques have been developed to generate sampling clocks at the receiver if the underlying semiconductor technology is not sufficient to generate clock speeds at the serial data rate. Specifically, multiple clocks with different phases are generated to sample the serial bit stream within a single clock cycle of the data rate. This technique of altering the phase of the clock relaxes the requirement to generate high-speed clocks on-chip. Although this technique reduces requisite maximum clock frequency, it still requires that the spacing of the clock edges for the multiple clock phases have a separation equal to ½ or less of the transmission bit time. If the receiver samples the bit stream four times per bit cycle, then the clock edges must be generated at the rate of ¼ of the transmission bit rate.
In high-speed serial links, one half the bit rate may equal a time less than the signal propagation delay time of a semiconductor. This is problematic because electronic designs typically generate multiple clock phases from one or more gate delays (e.g., inverters). To overcome this limitation, some electronic designers resort to techniques such as interpolation to achieve the required clock edge spacing. However, these techniques do not achieve low power dissipation and are sensitive to device offsets. Accordingly, it is desirable to develop a data and clock recovery technique that results in low power dissipation and is less sensitive to device offsets.